1. Field of the Invention
The invention relates generally to semiconductor circuits, and more particularly to a memory that allows faster data transfers than similar conventional memories, to systems that incorporate the memory, and to related data-transfer methods. In one embodiment, the memory generates an internal column address and receives an external column address during a page-mode data-transfer (read/write) cycle. By coupling the internal address to the column decoder instead of the external address, the memory can achieve a faster data-transfer speed. And by monitoring the external address, the memory allows the system to access a page of any length.
2. Description of the Background Art
The operating speeds of processor peripherals such as memory circuits often prevent engineers from designing faster digital-electronic systems. The speeds of microprocessors, which are at the hearts of today's digital systems, have increased dramatically within the last few years. But the speeds of today's memory circuits and other processor peripherals have lagged behind. Therefore, these slower peripherals typically limit the overall speed of a digital system because the system microprocessor must effectively “slow down” during transfers of data to and from these peripherals. That is, these slower peripherals are the “weak link in the chain”.
FIG. 1 is a timing diagram of a conventional fast-page-mode read cycle, which increases a memory's (memory not shown in FIG. 1) data-transfer speed by allowing a system (not shown in FIG. 1) to read multiple columns within a row, i.e., “page,” without reasserting the row address between reads. At time t0, the system asserts an active-low Row Address Strobe ( RAS) to latch the row address that the system has driven onto an external address bus. At time t1, the system drives the first column address onto the external address bus, and, at time t2, the system asserts an active-low Column Address Strobe ( CAS) to latch the first column address. At time t3, the data stored in the addressed memory location (not shown in FIG. 1) appears on the data bus. The system repeats these steps for subsequent column addresses until it reads data from all the desired memory locations within the addressed row. To exit the fast-page mode, the system transitions ( RAS) to an inactive high level (transition not shown in FIG. 1).
Unfortunately, latching an external column address for each data transfer limits the minimum fast-page-mode cycle time tpc, which is the minimum period of CAS that the memory manufacturer specifies for proper operation of the memory in fast-page mode. Each column address requires a minimum time ts—sometimes called the setup or precharge time—to propagate from the external address bus, through the memory's front-end circuitry (not shown in FIG. 1), to the column-address decoder (not shown in FIG. 1), where the system latches the column address by asserting CAS. Therefore, to prevent data-transfer errors, tpc must be long enough to account for ts. If, however, tpc is not long enough to account for ts, then the column-address decoder may latch an erroneous column address when the system asserts CAS; consequently, the system may end up reading data from the wrong memory location.
FIG. 2 is a timing diagram of a conventional nibble-mode read cycle, which allows faster data transfers than the fast-page-mode read cycle (FIG. 1) does because the memory (not shown in FIG. 2) generates the column addresses internally. As in the fast-page mode, the system (not shown in FIG. 2) asserts RAS at time t0 to latch the row address. At time t1, the system drives a first column base address onto the external address bus, and, at time t2, the system asserts CAS to latch this base address. An adder (not shown in FIG. 2) inside the memory sums a nibble count (here 00) with the base address to generate an initial column address, and, at time t3, the data stored at the generated column address appears on the data bus. Next, a nibble counter (not shown in FIG. 2) inside of the memory increments the nibble count, and the adder sums the incremented nibble count (here 01) with the base address to generate a first subsequent column address (not shown in FIG. 2). At time t4, the system asserts CAS to latch this subsequent column address into the address decoder (not shown in FIG. 2), and at time t5, the data stored in the addressed memory location appears on the data bus. The system continues asserting CAS until it has accessed a predetermined number—sometimes called a “nibble”—of columns (here four columns) within the row. To address a second nibble of columns within the same row, the system drives a second column base address (not shown in FIG. 2) onto the address bus and clocks CAS to repeat the cycle. Because the memory generates the subsequent column addresses internally, the minimum nibble-mode cycle time tnc (for all CAS cycles except the initial cycle) need not account for the external-address setup time ts (FIG. 1); consequently, tnc is typically shorter than the minimum fast-page-mode cycle time tpc. In one example, tpc is 60 nanoseconds (ns), and tnc for the same memory is 40 ns. Thus, the system can read data from the memory faster during the nibble mode than it can during the fast-page mode.
Unfortunately, because the number of columns in a nibble is typically fixed, reading data from more than one nibble of columns within a row often slows the data transfer by requiring the system to drive an additional column index address onto the external address bus for each additional nibble to be read. The nibble counter within the memory (neither shown in FIG. 2) typically has a fixed length (here two bits), therefore, if the system wants to read more than one nibble's worth (four columns here) of data from a row, it must execute multiple nibble-mode cycles. As stated above, the system must drive a column index address onto the external address bus at the beginning of each nibble-mode cycle. Because the column index address is on the external address bus, a setup time approximately equal to ts is required for the index address to propagate from the external address bus, through the memory's front-end circuitry, to the nibble adder (not shown in FIG. 1), and for the generated column address to propagate from the adder to the column-address decoder. Thus, the minimum nibble-mode cycle time for the first cycle is significantly longer than tnc, and may be as long or longer than the minimum page-mode cycle time tpc.
Furthermore, because a memory often does not allow the system to read a partial nibble, the number of columns the system reads often must be divisible by the number of columns in a nibble. For example, if there are four columns in a nibble, the number of columns the system can access during a nibble-mode cycle must be a multiple of four, i.e., 4, 8, 12, 16, . . .
Although fast-page- and nibble-mode read cycles are discussed above in conjunction with FIGS. 1 and 2, fast-page- and nibble-mode write cycles have similar problems.